1. Technical Field
The present invention relates to a semiconductor device with multilayer interconnect structure and to a manufacturing method thereof.
2. Related Art
With finer design adopted in semiconductor device, significant signal delay in metal interconnects has been observed and further improvement thereof is required. To countermeasure this delay, low dielectric constant film (Low-k film) is used as an insulating interlayer. The followings are configurations of conventional interconnects and via using Low-k film as an insulating interlayer.
FIG. 14 is a cross sectional view showing a configuration of a conventional semiconductor device. The semiconductor device 200 shown in FIG. 14 is manufactured by using the following process.
Firstly, an SiO2 film 201 and a barrier dielectric film 203 are formed on silicon substrate (not shown). The barrier dielectric film 203 is, for example, an SiC film or an SiCN film. On the barrier dielectric film 203, a porous SiOC film is formed in a film thickness of the order of 70 to 200 nm as a first Low-k film 205. On the first Low-k film 205, a hard mask SiO2 film (not shown) of approximately 50 to 150 nm is formed. Then, etching and ashing are performed through photolithography process using a fluorocarbon based gas for the hard mask SiO2 film and the porous SiOC film which is the first Low-k film 205 in order to form an interconnect trench. In the interconnect trench, a barrier metal film 211 and a copper interconnect 213 are formed, and then the SiCN or SiC film are formed as a barrier dielectric film 207. A porous SiOC film is formed thereon as a second Low-k film 209 and is similarly processed to form a via hole 215. This is how the semiconductor device 200 shown in FIG. 14 is configured. Afterward, a metal films is buried in the via hole 215 to form a via plug (not shown) The process is repeated to form a multilayered interconnect.
S. Nitta et al. (December 2004) “Successful Dual Damascene Integration of Extreme Low k Materials (k<2.0) Using a Novel Gap Fill Based Integration Scheme”, IEDM 2004 Proceedings, IEEE, U.S., and U.S. Pat. No. 6,413,852 disclose a configuration in which copper interconnects are formed firstly in porous Low-k film, another porous Low-k film is formed thereupon, and via is formed in the Low-k film. According to a technique described in these documents, a porous Low-k film is used as insulating film to lower the dielectric constant.